1. Field of the Invention
The invention relates to redundancy circuits for repairing a defective bit in a semiconductor memory device and, more particularly, relates to redundancy circuits for repairing a defective bit in a semiconductor memory device of a block dividing scheme.
2. Description of the Background Art
Generally, in a semiconductor memory device, spare rows and spare columns are provided for repairing a defective memory cell which does not function correctly (hereinafter referred to as defective bit) to increase the product yield.
FIG. 1 schematically shows a structure of a portion related to repairing of a defective bit in a conventional semiconductor memory device. The semiconductor memory device shown in the figure employs a column select line scheme and includes a shared sense amplifier structure. In the column select line scheme, when one column of memory cells arranged in an array of rows and columns is to be selected, the output (a column select signal) of a column decoder (column selecting means) is supplied to a column select line and a corresponding column of the memory cell array is connected to an internal data bus (IO line) with this column select line. In the shared sense amplifier structure, the memory cell array is divided into a plurality of blocks, the sense amplifier is provided to be shared by two blocks, and only one of the two blocks is selected tp be connected to the sense amplifier. The other block is maintained in a standby state (precharge state).
Referring to FIG. 1, the semiconductor memory device has a memory cell array 1 including a plurality of memory cells (not shown). The memory cell array 1 is divided into four memory cell blocks A, B, C and D. Each of the memory cell blocks A to D includes two subarrays 6a and 6b. Each of subarrays 6a and 6b has a plurality of memory cells arranged in a matrix including rows and columns though they are not specifically shown here.
The semiconductor memory device further includes a column decoder 3 for decoding internal column address signals A.sub.0 to A.sub.n from an address buffer (not shown) and generating column select signals and a column select line 40 for transmitting the column select signal from column decoder 3. Column select line 40 is provided for each of the outputs of column decoder 3 and runs over the four memory blocks A to D. Since the one column select line 40 is shared by four memory blocks A to D, the same column select signal is transmitted to each of memory cell blocks A to D.
The memory cell array 1 includes a spare column forming region 12 for repairing a column to which a defective bit is connected. Spare column forming region 12 is provided corresponding to each of subarrays 6a and 6b of memory cell blocks A to D. Spare column forming region 12 includes a word line WL extending from a corresponding subarray (6a or 6b) and a spare column select line 13 disposed to be shared by spare column forming region 12 for respective four memory cell blocks A to D. Spare column select line 13 selects a spare column (to which memory cells of one column are connected) formed in region 12. A spare column select signal is supplied to spare column select line 13 from column decoder 3 regardless that the spare column is selected or not.
A description will be made in the following supposing that one memory block includes subblocks 6a, 6b and the spare column forming region 12. The memory blocks A to D include (sense amplifier+I/O) blocks 2a, 2b, 2c, 2d formed between subarrays 6a and 6b, respectively. Each of (sense amplifier+I/O) blocks 2a to 2d is shared by the two subarrays 6a and 6b arranged on either side thereof. Blocks 2a to 2d include normal I/O line pairs 8a to 8d for transmitting read out data from a normal column (bit line pair) and spare I/O buses 9a to 9d for transmitting read out data from the spare column, respectively.
Detailed structures of (sense amplifier+I/O) blocks 2a to 2d are shown in FIGS. 2 and 3. FIG. 2 shows the detailed structure of a portion related to a normal column of (sense amplifier+I/O) block 2 (the reference number 2 is used for representatively indicating blocks 2a to 2d). The structure shown in FIG. 2 corresponds to a region 100 of FIG. 1.
Referring to FIG. 2, the portion related to the normal column of block 2 includes a sense amplifier circuit SA for differentially amplifying the potentials of the nodes N1 and N2, I/O gates Q5, Q6 formed of n channel MOS transistors, responsive to a column select signal on column select signal line 40 for connecting the nodes N1 and N2 to a normal I/O line pair 8, array selection gates Q1 and Q2 formed of n channel MOS transistors, responsive to a subarray select signal SL for connecting a bit line pair BLL, BLL of subarray 6a to sense amplifier nodes N1 and N2, respectively, and array selection gates Q3 and Q4 formed of n channel MOS transistors, responsive to a subarray select signal SR for connecting a bit line pair BLR, BLR of subarray 6b to sense amplifier nodes N1 and N2.
One column of the subarray has a pair of bit lines BLL, BLL or BLR, BLR. A memory cell MC is provided at a crossing of one word line WLL or WLR and one bit line of the bit line pair BLL, BLL or BLR, BLR. In FIG. 2, memory cells MC are provided at a crossing of word line WLL and bit line BLL and at a crossing of word line WLR and bit line BLR.
The subarray select signals SL, SR are generated in response to an address signal of one bit (for example, a most significant row address signal) and only one of them becomes active in operation.
A detailed structure of a portion related to the spare column of the (sense amplifier+I/O) block is shown in FIG. 3. The structure shown in FIG. 3 corresponds to a region 110 of FIG. 1. Referring to FIGS. 3, the spare column also includes a bit line pair SBLL, SBLL or SBLR, SBLR. The portion of block 2 related to the spare column includes a sense amplifier circuit SA for differentially amplifying the potentials of nodes N3 and N4, spare subarray selection gates Q7 and Q8 formed of n channel MOS transistors, responsive to a subarray select signal SL for connecting spare bit line pair SBLL, SBLL to sense amplifier nodes N3 and N4, spare subarray selection gates Q9 and Q10 formed of n channel MOS transistors, responsive to a subarray select signal SR for connecting spare bit line pair SBLR, SBLR to sense amplifier nodes N3 and N4, and spare I/O gates Q11 and Q12 formed of n channel MOS transistors, responsive to a spare column select signal on spare column select signal line 13 for connecting sense amplifier nodes N3 and N4 to a spare I/O line pair 9.
Referring back to FIG. 1, the semiconductor memory device includes fuse program circuits 10a to 10d provided corresponding to blocks A to D for determining if an address of a column including a defective bit in the related block (hereinafter referred to as defective column) is designated or not, and selection circuits 11a to 11d provided corresponding to blocks A to D, responsive to switching control signals .phi.A to .phi.D from the related fuse program circuit 10 (circuit 10a to 10d are representatively indicated by the reference numeral 10) for selecting one of the normal I/O line pair and spare I/O line 9 to connect the same to an internal data bus 120.
Fuse program circuit 10, for example, includes laser blowable fuse elements. An address of a defective bit (spare address) in an associated block is programmed by blowing off the fuse elements. Fuse program circuit 10 also determines coincidence/non coincidence between input address signals A.sub.0 to A.sub.n and the programmed spare address and generates switching control signals .phi.A to .phi.D indicating the result of the determination.
The semiconductor memory device further includes an output circuit 7a for amplifying data on an internal data bus 120 and generating external output data Q and an input circuit 7b for generating internal write data and transmitting the same to internal data bus 120 in accordance with external input data D. The operation thereof will now be described with reference to FIG. 4 which is a timing diagram of the operation.
Now let us assume that subarray 6a includes a word line which is active, that is, selected.
In the standby state, the subarray select signals SL, SR are both at "H", and bit line pairs BLL, BLL, BLR, BLR, SBLL, SBLL, SBLR, SBLR of each of blocks A to D are connected to sense amplifier nodes N1, N2, N3, N4 and precharged to an intermediate potential (for example, V.sub.cc /2, V.sub.cc : a power supply voltage level corresponding to "H").
When a row address signal is externally applied, subarray select signal SR rises to "L" at time t1 in accordance with this row address signal, gates Q3, Q4 and Q9, Q10 are turned off and subarray 6b and spare column region 12b are disconnected from sense amplifier nodes N1, N2 and N3, N4. Signal SL is at "H" and subarray 6a including the selected word line and spare column region 12a are connected to sense amplifier circuit of the block 2.
At time t2, the input row address signal is decoded in a decoder (not shown) and a corresponding word line WL is selected. Data of the memory cells connected to the selected word line are supplied to a corresponding bit line (BLL, BLL, SBLL, SBLL) in response to the word line selection. In FIG. 4, there is shown a case in which data of "H" is read out. In each bit line pair, the other bit line holds a precharge potential and a potential difference corresponding to the memory cell data read out is developed between the bit lines of each bit line pair.
At time t3, the sense amplifier circuit SA is activated and amplifies the bit line potential which has been supplied to nodes N1, N2 and N3, N4. At time t4, when the potential differences between the normal bit line pair BLL, BLL and between spare bit line pair SBLL, SBLL become sufficiently large by the sensing operation, column decoder 3 decodes supplied internal column address signals A.sub.0 to A.sub.3 and supplies a column select signal to corresponding column select line 40. At this time, a spare column select signal is also simultaneously supplied to spare column select signal line 13 from column decoder 3.
As a result, normal I/O line pair 8 is connected to selected normal bit line pair BLL, BLL and spare I/O line pair 9 is connected to spare bit line pair SBLL, SBLL. The potentials of normal I/O line pair 8 and spare I/O line pair 9 are changed from precharge potentials ("H") to levels corresponding to the signal potentials of the corresponding bit line pairs.
An address indicating a defective column (spare address) is programmed in fuse program circuit 10 in advance by blowing off a fuse. The fuse program circuit 10 compares input column address signals A.sub.0 to A.sub.n with the programmed spare address and generates control signals .phi.A to .phi.D according to the result of the comparison. Selection circuits 11a to 11d select normal I/O line pairs 8a to 8d when the corresponding control signals .phi.A to .phi.D indicate a non-coincidence. When they indicate a coincidence, spare I/O line pairs 9a to 9d are selected.
At the time of reading data, output circuit 7a is activated to amplify selected memory cell data transmitted to internal data bus 120 and generate external output data Q. At the time of writing data, input circuit 7b is activated to generate internal write data from the external write data D and supply the same to internal data bus 120. The internal write data is supplied to the selected memory cell through selection circuits 11a to 11d and blocks 2a to 2d. Since blocks A to D operate in parallel, input/output of data of 4 bits is carried out.
This semiconductor memory device has a disadvantage as follows. As a test operation for detecting a defective bit, there has been proposed a method in which data of the same value is written into all the memory cells, then memory cell data is read out, and the read out data is checked. In such a test mode, in order to speed up the test, row simultaneously writing is carried out in which data is simultaneous written into a row of memory cells. Subsequently, memory cell data of one row is simultaneously read out and a determination is made as to whether there is a defective bit in this one row by gate processing such as an exclusive NOR or the like in another path. A determination may be made as to whether there is a defective bit or not according to the potential level of I/O line 8 when memory cells of one row are simultaneously connected to normal I/O line 8. When there is a defective bit, a column is specified by sequentially accessing this row. The column address of the specified defective bit is programmed in fuse program circuits 10a to 10d, so that repairing of the defecting bit is effected. After programming the spare address, a test in the row simultaneous writing is conducted again in order to verify whether the repairing of the defective bit has been actually carried out or not. At this time, as the defective column is connected to normal I/O line 8, the test data is also written into the defective bit. Therefore, when the memory cell data is read out, the defective bit data is also read, so that the checking for the read out data indicates that there is a defective bit, making it impossible to determine if repairing of the defective bit has been certainly effected.
There is a test mode called a line mode test. In this test mode, data written in a memory cell of a column associated with a latch provided in each column is latched. Data in memory cells of one row is simultaneously read out and compared with data within a corresponding latch. Gate processing such as wired-AND processing is carried out for the result of the comparison of memory cells of one row, and a flag is produced indicating if there is a defective bit in the one row of memory cells. In this line mode test as well, the flag is generated reflecting the data of the defective bit, so that it is impossible to determine if the defective bit has been certainly repaired.
Additionally, in order to program a spare column in fuse program circuit 10, it is necessary to blow off a fuse element therein with a laser beam or the like. The number of fuse elements blown off is larger than the number of defective columns. At its maximum, in each of blocks A to D, it is necessary to blow off the same number of fuse elements as that of bits (n+1) of column address signals A.sub.0 to A.sub.n. An error tends to occur in programming the spare column and efficiency of repairing a defective bit is reduced.
Since different spare columns can be programmed in fuse program circuits 10a to 10d provided corresponding to blocks A to D, a defective column can be independently repaired in each block A to D. However, the selection circuit 11 and the fuse program circuit 10 must be provided for each block A to D, increasing the layout area and putting a serious obstacle to increasing density and integration of the semiconductor memory device.
Moreover, in fuse program circuit 10, it is necessary to detect a coincidence/non coincidence betweew the input address signal and the programmed spare column, then supply control signals .phi.A to .phi.O to selection circuit 11 and select I/O lines 8, 9, so that the access time is increased.
Furthermore, in each memory cycle, spare column select line 13 and spare I/O line 9 are accessed, so that power is wastefully consumed.
FIG. 5 is a diagram showing a structure of a main portion of another conventional semiconductor memory device. In FIG. 5, portions corresponding to those in the structure shown in FIG. 1 are given the same reference numerals.
The semiconductor memory device shown in FIG. 5 includes a switch circuit 4 provided between the outputs of a column decoder 3 and normal column select lines 40. Switch circuit 4 includes a switch element 14 provided between each of the outputs of column decoder 3 and a corresponding column select line 40, and a fuse element f accompanying each of switch elements 14. When the fuse element f is blown off, an associated switch element 14 becomes open, disconnecting the output of the column decoder 3 from column select line 40. Switch element 14, at the time of blowing off the associated fuse element f, also fixes the associated column select line 40 to "L" of a ground potential level, for example, and causes the column select line to be non-selected all the time. This semiconductor memory device also includes a spare column decoder 3a commonly provided in all the spare column forming regions 12 and a fuse program circuit 10 having a defective column address programmed through blown-off of the fuse elements therein. Fuse program circuit 10 determines a coincidence/non coincidence between input address signals A.sub.0 to A.sub.n and the programmed spare column address and supplies a signal .phi. indicating the result of the determination to spare column decoder 3a.
The structures and operation of the rest of the blocks 2a to 2d and so on are the same as those in the semiconductor memory device shown in FIG. 1 except that no spare I/O line is provided in regions 2a to 2d.
If an address of a column including a defective bit, i.e., a defective column address is specified in the test of the semiconductor memory device, the fuse element f of the corresponding switching element 14 is blown off and the defective column address (spare address) is programmed in fuse program circuit 10 through blown-off of the fuse element therein.
At the time of the operation of writing/reading data, even if a defective column is designated by internal column address signals A.sub.0 to A.sub.n, a column select signal is not supplied to a corresponding column select line 40. At this time, spare column decoder 3a is activated by a coincidence detecting signal from fuse program circuit 10 to supply a column select signal to a corresponding spare column select signal line 13. This spare column select signal causes a memory cell located at a crossing of the selected word line and the spare bit line pair in region 12 to be connected to I/O line pair 8.
In the semiconductor memory device shown in FIG. 5, only the columns that function normally are connected to I/O line pair 8, and a test mode such as the row simultaneous writing mode and the line mode test as stated above can be carried out in which a plurality of columns are simultaneously selected.
In the structure of FIG. 5 as well, however, the number of fuse elements to be blown off in order to program a spare column in fuse program circuit 10 is larger than that of defective columns. The maximum number of fuse elements to be blown off for programming is equal to the number of bits (n+1) of column address signals A.sub.0 to A.sub.n, causing an error to occur easily at the time of programming and reducing the efficiency of repairing defective bits.
Furthermore, as spare column decoder 3a is shared by blocks A to D, blocks A to D can have only the-same column address repaired. Since each of blocks A to D has a defective bit not repaired independently, spare column forming region 12 cannot be used effectively and the efficiency of repairing defective bits is reduced.
Additionally, as switch circuit 4 is provided between column decoder 3 and column select line 40 and fuse program circuit 10 is also needed, the layout area is increased.
Furthermore, spare column decoder 3a is activated after fuse program circuit 10 detects a coincidence/non coincidence of the internal column address signal, so that the access time becomes longer.
A structure in which defective bits are repaired without using a spare decoder and a particular spare column or row is disclosed in Japanese Patent Publication No. 61-35636 and Japanese Patent Laying-Open No. 61-61300.
Japanese Patent Publication No. 61-35636 discloses a memory including a switch circuit provided between each output of a decoder and each row or column. A connection path of the switch circuit is set by blowing off a fuse element inside the switch circuit. As a result, a large number of fuse elements are blown off and the efficiency of repairing defective bits is decreased.
Japanese Patent Laying-Open No. 61-61300 discloses a memory including a switch provided between each output of a decoder and a column or row. This switch is capable of selectively connecting one output of the decoder to one of a plurality of adjacent rows or columns. The defective row or column is disconnected from the decoder output and the output of the decoder is connected to an adjacent row or column through the switch.
Though both of the prior arts take account of repairing a defective bit in one memory cell array only, they have no regard for repairing of a defective bit on a block basis in a memory device of a block dividing scheme.